To be completed in C++

Part I
4 bit counter

Create a 4 bit down counter that counts down from 9 to zero and then count 10. 11, 12 and then back to 9. You will design the logic of the circuit and also a chip level diagram. Your circuit will have a 4 bit output. It will be a finite state machine:

Any input to your circuit other than zero through nine (0000 1001) ten, eleven and twelve(10101100), should reset the output to nine (1001). Your tasks are to document the following. Create a state transition diagram for your finite state machine based counter (do not forget transitions to state nine from unused states)
1.    Specify the truth table (assuming D Flip Flops).
2.    Derive necessary Boolean equations (using kmaps)
3.    Draw gate-level logic diagram (logic gate symbols).
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Part II
2 bit integer division circuit

Design and implement a 2-bit integer division circuit. The circuit has four inputs A1, A0, B1, B0 and five outputs Q1, Q0, R1, R0, E. The values on A1, A0 and B1, B0 are treated as unsigned binary integer number A and B respectively:

The circuit should generate the quotient Q and remainder R of the division A/B on lines Q1, Q0 and R1, R0 respectively. If division by zero is attempted, line E is set ‘1’ (else E is ‘0’) and the values on lines Q1, Q0, R1, R0 are considered invalid. Your tasks are to document the following.
1.    Specify the truth table.
2.    Derive necessary Boolean equations (using kmaps)
3.    Draw gate-level logic diagram (logic gate symbols).

Attached document contains diagrams.